1. Field of Invention
The present invention relates to multiplexer structures for use with programmable logic devices or other similar devices.
2. Description of Related Art
Programmable logic devices (PLDs) (also sometimes referred to as CPLDs, PALs, PLAs, FPLAs, EPLDs, EEPLDs, LCAs, FPGAs, or by other names), are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices are well known in the art and typically provide an “off the shelf” device having at least a portion that can be electrically programmed to meet a user's specific needs. Application specific integrated circuits (ASICs) have traditionally been fixed integrated circuits, however, it is possible to provide an ASIC that has a portion or portions that are programmable; thus, it is possible for an integrated circuit device to have qualities of both an ASIC and a PLD. The term PLD as used herein will be considered broad enough to include such devices.
PLDs typically contain a large number of multiplexers to select signals from various routing and logic elements, with the input being selected controlled by a number of configuration RAM (C-RAM) bits. Each such multiplexer consists of a number of stages, typically two, where each stage includes a network of pass transistors followed by one or more buffers. Most of the delay and area of a PLD typically relates to the corresponding multiplexers, and so their speed and area are often critically important. Another important factor in constructing such multiplexers is the ability to make electrical connections to the input of a multiplexer independently of the connections to any other multiplexer on the PLD. Although there are some places in the PLD where it may be desirable to have two multiplexers share a common set of inputs, in other areas (such as general routing between logic elements on the PLD) it is preferable that the inputs to each multiplexer be chosen independently.
Conventional multiplexer designs are often limited by inefficient layouts. In some designs, for example, multiple diffusion regions are laid out to form transistor sources and drains, but gaps between them are provided so that the sources and drains are electrically isolated, thereby wasting area and causing increased parasitic capacitance that leads to system delays. In general for MOS transistors, the diffusion area and diffusion perimeter each contribute capacitance to the source and drain nodes. If the transistors in a multiplexer are constructed completely independently, then each transistor will have a full diffusion capacitance connected to each of the source and drain.
According to one alternative approach involving a pair of multiplexers, transistors are laid out using a continuous strip of diffusion, and alternate transistors share source/drain diffusions thereby reducing capacitance. In this approach, however, each input signal goes to both of the multiplexers thereby limiting the effectiveness of the design by restricting the ability to independently choose the connectivity of inputs to multiplexers. (U.S. Pat. No. 6,020,776)
Another concern particular to PLDs is the pitch of the transistors, that is, the spacing between the gates of adjacent transistors. Because the gates of the pass transistors are connected to the C-RAM cells and there are a number of pass transistors laid out in close proximity, it is desirable that the pitch of the pass transistors be similar to the width (or height) of the C-RAMs. C-RAMs are conventionally several times wider than the pitch of minimum spaced gates of transistors. Sharing diffusions reduces the pitch of the gates and if the resulting pitch of transistors per C-RAM is small, it may be necessary to use extra wiring to connect the C-RAMs to the pass transistors, or there may be wasted space if the transistors are constrained to line up with the C-RAM. This type of awkward layout also can lead to an inefficient use of available area.
Thus, there is a need for multiplexer structures that include shared diffusion regions for sources and drains of transistors while avoiding restrictions associated with constrained inputs and awkward layouts.